FPGA design engineering

One of the classes I’m TAing for is basically intro to FPGA design engineering. I show the students how to plug things in, where to right-click for menus, so on and so forth. Verilog is written in the accusative case, passive voice.

But I’ve never had much academic instruction in digital logic, not the theory beyond truth tables. So my experience is wildly disjoint from the class. The prof went over Karnaugh maps, and the students were all bored. They’d seen it a dozen times. I had never even heard of this stuff.

Meanwhile they’re assigning A to B, not knowing an assign statement reads right to left.

Weird stuff. The consequence of going back to school after having been out in the world for a few years.

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